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| ? semiconductor components industries, llc, 2015 november, 2015 ? rev. 2 1 publication order number: tcc?202/d TCC-202 two-output ptic control ic introduction tcc?202 is a two?output high?voltage digital to analog control ic specifically designed to control and bias on semiconductor?s passive tunable integrated circuits (ptics). these tunable capacitor control circuits are intended for use in mobile phones and dedicated rf tuning applications. the implementation of on semiconductor?s tunable circuits in mobile phones enables significant improvement in terms of antenna radiated performance. the tunable capacitors are controlled through a bias voltage ranging from 1 v to 24 v. the tcc?202 high?voltage ptic control ic has been specifically designed to cover this need, providing two independent high?voltage outputs that control up to two different tunable ptics in parallel. the device is fully controlled through a mipi interface. key features ? controls on semiconductor?s ptic tunable capacitors ? compliant with timing needs of cellular and other wireless system requirements ? integrated boost converter with 2 programmable dac outputs (up to 24 v) ? low power consumption ? mipi?rffe interface ? compliant with mipi 26 mhz read?back ? available in wlcsp (rdl ball arrays) ? this is a pb?free device typical applications ? multi?band, multi?standard, advanced and simple mobile phones ? tunable antenna matching networks ? compatible with closed?loop and open?loop antenna tuner applications www. onsemi.com see detailed ordering and shipping information on page 21 o f this data sheet. ordering information marking diagram wlcsp12 case 567kz a = assembly location l = wafer lot y = year w = work week = pb?free package xxxx alyw
tcc?202 www. onsemi.com 2 figure 1. control ic functional block diagram vio vdda l_boost vhv vreg gnd_boost clk data outa 7 bit dac otp level shifter vio por vreg por start reference interface registers booster outb 7 bit dac regulator 4 bit dac bandgap gnd atest vio_on por_vreg 7 7 ibias_start / vref_start vio vdda vreg vhv rc osc level shifter figure 2. die bump side view a4 b4 c4 a3 b3 c3 a2 b2 c2 a1 b1 c1 tcc?202 www. onsemi.com 3 rdl pin out table 1. pad descriptions bump rdl name type description max voltage a1 outb aoh high voltage output b vhv a2 atest ao analog test out (note 1) vreg a3 vhv aoh/aih boost high voltage 28 a4 l_boost aoh boost inductor 28 b1 outa aoh high voltage output a vhv b2 gnda p analog ground 0 b3 gnd_boost p ground for booster 0 b4 vio digital io supply 2 c1 vreg ao regulator output 2 c2 avdd analog supply 5.5 c3 data dio mipi rffe data vio c4 clk di mipi rffe clock vio 1. to be grounded when not in use. electrical performance specifications table 2. absolute maximum ratings symbol parameter rating unit avdd analog supply voltage ?0.3 to +6.0 v vio io reference supply voltage ?0.3 to +2.2 v v i/o input voltage logic lines (data, clk, cs) ?0.3 to vio + 0.3 v v hvh vhv maximum voltage ?0.3 to 30 v v esd (hbm) human body model, jesd22?a114, all i/o 2,000 v v esd (mm) machine model, jesd22?a115 200 v t stg storage temperature ?55 to +150 c t amb_op_max max operating ambient temperature without damage +110 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. tcc?202 www. onsemi.com 4 table 3. recomended operating conditions symbol parameter rating unit min typ max t amb_ op operating ambient temperature ?30 ? +85 c t j_ op operating junction temperature ?30 ? +125 c avdd analog supply voltage 2.3 ? 5.5 v vio io reference supply voltage 1.62 ? 1.98 v table 4. dc characteristics (t a = ?30 to +85 c; v outx = 15 v for each output; 2.3 v < avdd < 5.5 v; 1.62 v < vio < 1.98 v; r load = equivalent series load of 5.6 k and 2.7 nf; c hv = 47 nf; l boost = 15 h; unless otherwise specified) symbol parameter min typ max unit comment shutdown mode i avdd avdd supply current ? ? 1.5 a vio supply is low i l_ boost l_boost leakage ? ? 1.5 i batt battery current ? ? 2.5 i vio vio supply current ?1 ? 1 i clk clk leakage ?1 ? 1 i data data leakage ?1 ? 1 active mode i batt_ ss0 average battery current, 2 outputs @ 0 v steady state ? 380 750 a at vhv = 20 v avdd = 3.3 v i bat_ ss2 average battery current, 2 outputs @ 2 v steady state ? 400 780 a at vhv = 20 v avdd = 3.3 v i batt_ ss16 average battery current, 2 outputs @ 16 v steady state ? 510 870 at vhv = 20 v avdd = 3.3 v i l_ boost_ ss0 average inductor current, 2 outputs @ 0 v steady state ? 260 490 at vhv = 20 v avdd = 3.3 v i l_ boost_ ss2 average inductor current, 2 outputs @ 2 v steady state ? 280 510 at vhv = 20 v avdd = 3.3 v i l_ boost_ ss16 average inductor current, 2 outputs @ 16 v steady state ? 400 600 at vhv = 20 v avdd = 3.3 v i vio_ inact vio average inactive current ? ? 3 vio is high, no bus activity i vio_ active vio average active current ? ? 250 vio = 1.8 v, master sending data at 26 mhz v vreg 1.7 ? 1.9 v no external load allowed low power mode i avdd avdd supply current ? ? 8 a i l_ boost l_boost leakage ? ? 6 i batt battery current ? ? 14 i avdd + i l_ boost i vio vio supply current ? ? 3 no bus activity v vreg 1.6 ? 1.9 v no external load allowed tcc?202 www. onsemi.com 5 table 5. boost converter characteristics (avdd from 2.3 v to 5.5 v; vio from 1.62 v to 1.98 v; t a = ?30 to +85 c; c hv = 47 nf; l boost = 15 h; unless otherwise specified) symbol parameter conditions min typ max unit vhv_min minimum programmable output volt- age (average), dac boost = 0h active mode ? 13 ? v vhv_max maximum programmable output volt- age (average), dac boost = fh active mode ? 28 ? resolution boost voltage resolution 4?bit dac ? 1 ? i l_ boost_ limit inductor current limit ? 200 ? ma table 6. analog outputs (out a, out b) (avdd from 2.3 v to 5.5 v; vio from 1.62 v to 1.98 v; vhv = 26 v; t a = ?30 to +85 c; rload = unless otherwise specified) parameter description min typ max unit comment shutdown mode z out out a, out b output impedance 7 ? ? m dac disabled active mode v oh maximum output voltage ? 23.8 ? v dac a, b = 7fh, dac boost = fh, i oh < 10 a v ol minimum output voltage ? ? 1 v dac a, b = 01h, dac boost = 0h to fh, i oh < 10 a slew rate ? 3 10 s 2 v to 24 v step, measured at v out = 15.2 v, r load = equivalent series load of 2.7 k and 5.6 nf, turbo enabled r pd out a, out b set in pull?down mode ? ? 1000 dac a, b = 00h, dac boost = 0h to fh, selected output(s) is disabled resolution voltage resolution (1?bit) ? 188 ? mv (1 lsb = 1?bit) v offset zero scale, least squared best fit ?1 ? +1 lsb error ?3.0 ? +3.0 %v out over 2 v ? 24 v v o range dnl differential non?linearity least squared best fit ?0.9 ? +0.9 lsb over 2 v ? 24 v v o range inl integral non?linearity least squared best fit ?1 ? +1 lsb over 2 v ? 24 v v o range i sc over current protection ? 5 65 ma any dac output shorted to ground v ripple output ripple with all outputs at steady state ? ? 40 mv rms over 2 v ? 24 v for vhv = 23.5 v tcc?202 www. onsemi.com 6 theory of operation overview the control ic outputs are directly controlled by programming the two dacs (dac a and dac b) through the digital interface. the dac stages are driven from a reference voltage, generating an analog output voltage driving a high?voltage amplifier supplied from the boost converter (see figure 1 ? control ic functional block diagram). the control ic output voltages are scaled from 0 v to 24 v, with 128 steps of 188 mv (2x (24 / 255 v) = 0.188235 v). the nominal control ic output can be approximated to 188 mv x dac value. for performance optimization the boost output voltage (vhv) can be programmed to levels between 13 v and 28 v via the dac_boost register (4 bits with 1 v steps). the startup default level for the boosted voltage is vhv = 24 v. for proper operation and to avoid saturation of the output devices and noise issues it is recommended to operate the boosted vhv voltage at least 2 v above the highest programmed v out voltage of any of the two outputs. operating modes the following operating modes are available: 1. shutdown mode: all circuit blocks are off, the dac outputs are disabled and placed in high z state and current consumption is limited to minimal leakage current. the shutdown mode is entered upon initial application of avdd or upon vio being placed in the low state. the contents of the registers are not maintained in shutdown mode. 2. startup mode: startup is only a transitory mode. startup mode is entered upon a vio high state. in startup mode all registers are reset to their default states, the digital interface is functional, the boost converter is activated, outputs out a and out b are disabled and the dac outputs are placed in a high z state. control software can request a full hardware and register reset of the tcc?202 by sending an appropriate pwr_mode command to direct the chip from either the active mode or the low power mode to the startup mode. from the startup mode the device automatically pro ceeds to the active mode. 3. active mode: all blocks of the tcc?202 are activated and the dac outputs are fully controlled through the digital interface, dacs remain off until enabled. the dac settings can be dynamically modified and the hv outputs will be adjusted according to the specified timing diagrams. each dac can be individually controlled and/or switched off according to application requirements. active mode is automatically entered from the startup mode. active mode can also be entered from the low power mode under control software command. 4. low power mode: in low power mode the serial interface stays enabled, the dac outputs are disabled and are placed in a high z state and the boost voltage circuit is disabled. control software can request to enter the low power mode from the active mode by sending an appropriate pwr_mode command. the contents of all registers are maintained in the low power mode. shutdown startup (registers reset) active low power (user defined) pwr_mode = 0b10 vdda = 0 figure 3. modes of operation battery insertion (user defined) pwr_mode = 0b01 automatic vio = high vio = low vio = low pwr_mode = 0b00 pwr_mode = 0b01 tcc?202 www. onsemi.com 7 avdd power?on reset (por) upon application of avdd the tcc?202 will be in shutdown mode. all circuit blocks are off and the chip draws only minimal leakage current. vio power?on reset and startup conditions a high level on vio places the chip in startup mode which provides a por to the tcc?202. por resets all registers to their default settings as described in table 8. vio por also resets the serial interface circuitry. por is not a brown?out detector and vio needs to be brought back to a low level to enable the por to trigger again. table 7. vio power?on reset and startup register default state for vio por comment dac boost [1011] vhv = 24 v power mode [01]>[00] transitions from shutdown to startup and then automatically to active mode dac enable [000000] v out a, b disabled dac a output in high?z mode dac b output in high?z mode vio shutdown a low level at any time on vio places the chip in shutdown mode in which all circuit blocks are off. the contents of the registers are not maintained in shutdown mode. table 8. vio thresholds (avdd from 2.3 v to 5.5 v; t a = ?30 to +85 c unless otherwise specified) parameter description min typ max unit comments viorst vio low threshold ? ? 0.2 v when vio is lowered below this threshold level the chip is reset and placed into the shutdown state power supply sequencing the avdd input is typically directly supplied from the battery an d thus is the first on. after avdd is applied and before vio is applied to the chip, all circuits are in the shutdown stat e and draw minimum leakage cu rrents. upon application of vio, the chip automatically starts up using default settings and is placed in the active state waiting for a command via the serial interface . table 9. timing (avdd from 2.3 v to 5.5 v; vio from 1.62 v to 1.98 v; t a = ?30 to +85 c; out a and out b; chv = 47 nf; l boost = 15 h; vhv = 24 v; turbo?charge mode off unless othe rwise specified; vdda = 1.7 v) parameter description min typ max unit comments t por_ vreg internal bias settling time from shutdown to active mode ? 50 120 s for info only t boost_ start time to charge chv @ 80% of set vhv (set to 24 v, v dda = 2.7 v) ? 130 ? s for info only t sd_ to_ act startup time from shutdown to active mode ? 180 300 s t set+ output a, b positive settling time to within 5% of the delta voltage, equivalent series load of 5.6 k and 2.7 nf, v out from 2 v to 20 v; 0bh (11d) to 55h (85d) ? 50 60 s voltage settling time connected on v out a, b t set? output a, b negative settling time to within 5% of the delta voltage, equivalent series load of 5.6 k and 2.7 nf, v out from 20 v to 2 v; 55h (85d) to 0bh (11d) ? 50 60 s voltage settling time connected on v out a, b t set+ output a, b positive settling time with turbo ? 35 ? s voltage settling time connected on v out a, b t set? output a, b negative settling time with turbo ? 35 ? s voltage settling time connected on v out a, b tcc?202 www. onsemi.com 8 figure 4. output settling diagram figure 5. startup timing diagram tcc?202 www. onsemi.com 9 boost control the tcc?202 integrates an asynchronous current control boost converter. it operates in a discontinuous mode and features spread?spectrum circuitry for electro?magnetic interference (emi) reduction. the average boost clock is 2 mhz and the clock is spread between 0.8 mhz and 4 mhz. boost output voltage (vhv) control principle the asynchronous control starts the boost converter as soon as the vhv voltage drops below the reference set by the 4?bit dac and stops the boost converter when the vhv voltage rises above the reference again. due to the slow response time of the control loop, the vhv voltage may drop below the set voltage before the control loop compensates for it. in the same manner, vhv can rise higher than the set value. this effect may reduce the maximum output voltage available. please refer to figure 7 below. the asynchronous control reduces switching losses and improves the output (vhv) regulation of the dc/dc converter under light load, particularly in the situation where the tcc?202 only maintains the output voltages to fixed values. s- e- t v- h- v figure 6. vhv voltage waveform vhv time delay delay chv discharge delay chv recharge boost running high impedance (high z) feature in shutdown mode the out pins are set to a high impedance mode (high z). following is the principle of operation for the control ic: 1. the dac output voltage v out is defined by: v out dac code 255 24 v 2 (eq. 1) 2. the voltage vhv defines the maximum supply voltage of the dac supply output regulator and is set by a 4?bit control. 3. the maximum dac dc output voltage v out is limited to (vhv ? 2 v). 4. the minimum output dac voltage v out is 1.0 v max. figure 7. dac output range example a figure 8. dac output range example b digital interface the control ic is fully controlled through a mipi rffe?compliant digital interface the digital interface is described in the following sections of this document, for detailed programming instructions please refer to the programming guide, available by contacting on semiconductor. tcc?202 www. onsemi.com 10 turbo?charge mode the tcc?202 control ic has a turbo?char ge mode that significantly shortens the system settling time when changing programming voltages. in turbo?char ge mode the dac output target voltage is temporarily set to either a delta voltage above or a delta voltage below the actual desired target for the tcdly time. it is recommended that v hv be set to 24 v when using t urbo?charge mode. glide mode unlike turbo mode, which is intended to reduce the charging time, the glide mode extends the transition time of each dac output. each dac has an individual control for turbo mode, glide mode or regular voltage switching. the glide mode can be enabled for a particular dac through the index register, by setting dac state to ?1? when glide mode is enabled, turbo mode is off for a particular dac, but one dac can be gliding while the other is turbo. during glide mode the output voltage of a dac is either increased or dec reased to its set end point, in max 255 steps, where each dac time step can be programmed between 2 s to 64 s. for programming the glide mode refer to the application note (coming soon). a programming input is not required to maintain a glide transition, all step controls are maintained by the part. only the inputs to define the glide need to be programmed. rf front?end control interface (mipi rffe interface) the tcc?202 is a read/write slave device which is fully compliant to the mipi alliance specification for rf front?end control interface (rffe) version 1.10.00 26 july 2011. this device is rated at full?speed operation for 1.62 v tcc?202 www. onsemi.com 12 table 12. register details the following are the details of the available rffe registers: register rffe: rffe_reg_0x00 address rffe a[4:0]: 0x00 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 6 5 4 3 2 1 0 bits ss enable reserved reserved dac a (note 6) dac b (note 6) reserved reserved reset w?1 u?0 u?0 w?0 w?0 u?0 u?0 6. when any of the bits [3:2] are written with ?0?, the corres ponding dac is disabled, but the turbo?charge process which is alr eady started, will not be stopped. 7. if all bits [3:2] are ?0?, then incoming dac messages will be ignored, until at least one of [3:1] is set ?1?. bit [6]: spread spectrum enable 0: ss disabled 1: ss enabled bit [3]: control dac a 0: off (default) 1: enabled bit [2]: control dac b 0: off (default) 1: enabled register rffe: rffe_reg_0x01 address rffe a[4:0]: 0x01 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits reserved reset w?0 w?0 w?0 w?0 w?0 w?0 w?0 w?0 register rffe: rffe_reg_0x02 address rffe a[4:0]: 0x02 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits reserved dac a value [6:0] reset u?0 w?0 w?0 w?0 w?0 w?0 w?0 w?0 register rffe: rffe_reg_0x03 address rffe a[4:0]: 0x03 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits not used dac b value [6:0] reset w?0 w?0 w?0 w?0 w?0 w?0 w?0 w?0 tc_stp_dacx [1:0] turbo steps for tcdly [us] 00 3 01 (default) 5 10 7 11 9 register rffe: rffe_reg_0x12 address rffe a[4:0]: 0x12 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits reserved reserved tc_stp_dac_b tc_stp_dac_a reset u?0 u?0 u?0 u?0 w?0 w?1 w?0 w?1 tcc?202 www. onsemi.com 13 register rffe: rffe_reg_0x13 address rffe a[4:0]: 0x13 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits reserved reserved tcm_b tcm_a reset u?0 u?0 u?0 u?0 w?0 w?0 w?0 w?0 tcm [1:0] turbo multiplication factor 00 (default) 4 01 3 10 2 11 1 step [us] dac state 0 1 2 3 4 5 6 7 8 9 10 11 9 tcdly turbo off 18 27 36 45 54 63 72 81 90 99 7 tcdly turbo off 14 21 28 35 42 49 56 63 70 77 5 (default) tcdly turbo off 10 15 20 25 30 35 40 45 50 55 3 tcdly turbo off 6 9 12 15 18 21 24 27 30 33 the value of turbo time is deducted based on the hardware comparison of new dac value in respect to old dac value , as follows: if dac new > dac old , then t up = tcdly if dac new < dac old , and dac new_divby2 < 21 , then t down = tcdly + tcm * (21 ? dac _new_divby2) if dac new < dac old , and dac new_divby2 > 21 , then t down = tcdly if dac new < dac old , and dac new_divby2 = 21 , then t down = tcdly register rffe: rffe_reg_0x9 address rffe a[4:0]: 0x09 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits reserved dac_wakeup_ctrl turbo latency select reserved reserved reset u?0 u?0 u?0 u?0 w?0 w?0 w?0 w?0 bit [3]: dac wake?up control applicable to wake?up from lp 0 : (default) don?t apply turbo when wake?up from lp std or lp fta 1: always apply turbo up when wake?up from lp std or lp fta. turbo up is calculated based on dac value prior to enter lp std or lp fta mode. note 1: turbo is not applied after wake?up to the dacs which are programmed with 0x00 in the dac value register note 2: t urbo is not applied after wake?up from fta mode if a trigger (t urbo, normal, glide) was generated while tc2x2 was in lp fta mode note 3: when bit[3] = ?1?, then t urbo is applied after wake?up regardless if: ? dac values are updated or not ? last dac value update is equal with old dac value note 4: when rffe_reg_0x31 / wake?up dac ctrl is ?0? (default) turbo after wake?up is applied after first vhv_too_lowfalling edge is detected. when rffe_reg_0x31 / w ake?up dac ctrl is ?1? t urbo after wake?up is applied after rc_clk starts. bit [2]: turbo up latency select when wake?up from lp. this field has no effect when dac_wakeup_ctrl[1:0] = ?00? 0: (default) turbo up latency is 50 s 1: turbo up latency is 100 s tcc?202 www. onsemi.com 14 register rffe: rffe_reg_0x10 address rffe a[4:0]: 0x10 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits reserved fixed boost voltage value reset u?0 u?0 u?0 u?1 w - 1 w?0 w - 1 w - 1 bit [3:0]: boost voltage value register rffe: rffe_status_0x1a address rffe a[4:0]: 0x1a reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits swr cfpe cle afpe dfpe rure wure bge reset w?0 r?0 r?0 r?0 r?0 r?0 r?0 r?0 rffe_status register can be read any time after power?up without the need to enable the read operation as described below. swr soft?reset mipi?rffe registers write ?1? to this bit to reset all the mipi?rffe registers, except rffe_reg_0x1c, rffe_usid, and rffe_group_sid this bit will always read?back ?0?. the soft reset occurs in the last clock cycle of the mipi?rffe frame which writes ?1? to this bit. right immediately after this frame, all the mipi?rffe registers have the reset value and are ready to be reprogrammed as desired. the otp duplicated registers are reset to the values written in otp. swr can be written only by usid messages. gsid and broadcast frames will be ignored when writing to this register field. rffe_status bits [6:0] are set ?1? by hardware to flag when a certain condition is detected, as described below. rffe_status bits [6:0] cannot be written, but it is cleared to ?0? under following conditions: ? hardware self?reset is applied after rffe_status is read ? when swr is written ?1? with usid frames ? when power mode transitions through startup mode ?01? ? after power?up reset cfpe 1: command frame with parity error received. on the occurrence of this error, the slave will ignore the entire command sequence cle 1: incompatible command length, due to unexpected ssc received before command length to be completed. on the occurrence of this error, the slave will accept write data up to the last correct and complete frame. when mipi?rffe multi?byte read command is detected, the slave will always replay with an extended read command of length of one byte. afpe 1: address frame with parity error received. on the occurrence of this error, the slave will ignore the entire command sequence dfpe 1: data frame with parity error received. on the occurrence of this error, the slave will ignore only the erroneous data byte (s) rure 1: read of non?existent register was detected. on the occurrence of this error, the slave will not respond to the read command frame. when the read operation is not enabled ,any read from an address other than 0x1a, will set rure and the slave will not respond to the read command frame. when the read operation is enabled , any read from an unoccupied rffe register address will set rure. wure 1: write to non?existent register was detected. on the occurrence of this error, the slave discards data being written, and on the next received frame, proceeds as normal bge 1: read using the broadcast id was detected on the occurrence of this error, the slave will ignore the entire command sequence tcc?202 www. onsemi.com 15 register rffe: rffe_group_sid_0x1b address rffe a[4:0]: 0x1b reset source: nreset_dig or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits reserved reserved reserved reserved gsid[3] gsid[2] gsid[1] gsid[ 0 ] reset 0 0 0 0 w?0 w?0 w?0 w?0 gsid = group slave identifier register note: the gsid[3:0] field can be written directly by messages using usid. note: gsid value is not retained during shutdown power mode. note: gsid value is not affected by swr bit from rffe_status register note: frames using usid = gsid, can write only to rffe_reg_0x1c[7:6] and [2:0]. note: rffe read frames containing gsid will be ignored register rffe: rffe_reg_0x1c address rffe a[4:0]: 0x1c reset source: nreset_dig or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits power mode (note 12) trigger mask 2 (notes 8, 9, 10, 11) trigger mask 1 (notes 8, 9, 10, 11) trigger mask 0 (notes 8, 9, 10, 11) trigger 2 trigger 1 trigger 0 reset w?0 w?0 w?0 w?0 w?0 w?0 w?0 w?0 8. trigger mask bits [5:3] can be changed, either set or cleared, only with an individual message using usid 9. during broadcast mipi?rffe accesses using gsid = ?0000?, trigger bits [2:0] are masked by the pre?existent setting of trigger mask bits [5:3] 10. during individual mipi?rffe accesses using usid, trigger bits [2:0] are masked by the incoming trigger mask bits [5:3] withi n the same write message to rffe_reg_0x1c register. during individual mipi?rffe accesses using usid, pre?existent setting of t rigger mask bits [5:3] is ignored. 11. when rffe_reg_0x1c/ trigger_mask_2 = ?1? and trigger_mask_1 = ?1? and trigger_mask_0 = ?1?, then dac messages will be sent t o dacs immediately after rffe_reg_0x04 is received, without waiting for any trigger 12. power mode field bits [7:6] and triggers bits [2:0] can be changed by either mipi?rffe broadcast messages when usid field wi thin the register write command is 0x0 , or individual messages when us id fields within the register write command is equal with rffe_reg_0x1f[3:0] note: all the 8 bits of rffe_reg_0x1c register bits are notaffected by swr bit from rffe_status register bit [7:6]: power mode 00: active mode, defined by following hardware behavior: ? boost control active, vhv set by digital interface ? vout a and b enabled and controlled by digital interface 01: startup mode, defined by following hardware behavior: o ? boost control active, vhv set by digital interface ? vout a and b disabled 10: low power mode is defined by following hardware behavior: ? digital interface is active, while all other circuits are in lowpower mode 11: reserved (state of hardware does not change) bit 5: mask trigger 2 0:trigger 2 not masked. data goes to destination register after bit 2 is written value 1 (default) 1:trigger 2 is masked. data goes directly to the destination register bit 4: mask trigger 1 0:trigger 1 not masked. data goes to destination register after bit 1 is written value 1(default) 1:trigger 1 is masked. data goes directly to the destination register. bit 3: mask trigger 0 0:trigger 0 not masked. data goes to destination register after bit 0 is written value 1(default) 1:trigger 0 is masked. data goes directly to the destination register. bit 2: trigger 2 write 1 to this bit, to move data from shadowregisters into destination register. this trigger can be masked by bit 5. bit 1: trigger 1 write 1 to this bit, to move data from shadowregisters into destination register. this trigger can be masked by bit 4. bit 0: trigger 0 write 1 to this bit, to move data from shadowregisters into destination register. this trigger can be masked by bit 3. tcc?202 www. onsemi.com 16 register rffe: rffe_product_id_0x1d address rffe a[4:0]: 0x1d reset source: n/a 7 6 5 4 3 2 1 0 bits pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 (1) reset 0 0 1 0 0 0 0 otp[4] bits [7:1] are hardcoded in asic bits [0] can be programmed in otp during manufacturing register rffe: rffe_manufacturer_id_0x1e address rffe a[4:0]: 0x1e reset source: n/a 7 6 5 4 3 2 1 0 bits mpn7 mpn6 mpn5 mpn4 mpn3 mpn2 mpn1 mpn0 reset 0 0 1 0 1 1 1 0 register rffe: rffe_usid_0x1f address rffe a[4:0]: 0x1f reset source: nreset_dig or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits reserved (2) mpn9 (2) mpn8 (2) usid3 (1) usid2 (1) usid1 (1) usid0 (1) reset 0 0 0 1 w?0 w?1 w?1 w?1 usid = unique slave identifier register 1. usid field can be changed by: ? mipi?rffe broadcast messages when usid field within the register write command is 0b0000 ? mipi?rffe individual messages when usid field within the register write command equal with content of rffe_reg_0x1f[3:0] 2. in the sequence of writing usid field, the upper [7:4] must match the value 0b0001 hardcoded in the rffe register 0x1f note: usid value is not retained during shutdown power mode. note: usid value is not affected by swr bit from rffe_status register. tcc?202 www. onsemi.com 17 register 0 write command sequence the command sequence starts with an ssc which is followed by the register 0 write command frame. this frame contains the slave address, a logic one, and the seven bit word that will be written to register 0. the command sequence is depicted below. figure 12. register 0 write command sequence table 13. rffe command frame for register 0 write command sequence description ssc command frame dac configuration 1 0 sa (3,0) 1 0 0 0 0 0 0 0 p bp register write command sequence the write register command sequence may be used to access each register (addresses 0?31). figure 13. register write command sequence table 14. rffe command frame for register write command sequence for dacs loading procedure description ssc command frame data frame bp turbo charge settings 1 0 sa (3,0) 0 1 0 0 0 0 0 1 p turbo charge (7:0) p bp register write dac a 1 0 sa (3,0) 0 1 0 0 0 0 1 0 p dac_a (6:0) p bp register write dac b 1 0 sa (3:0) 0 1 0 0 0 0 1 1 p dac_b (6:0) p bp tcc?202 www. onsemi.com 18 this sequence can be used for read/write procedure for some other purposes as shown on the following table: table 15. other rffe command sequences description ssc command frame data frame active mode 1 0 sa (3,0) 0 1 0 1 1 1 0 0 p 0 0 x x x x x x bp startup mode 1 0 sa (3,0) 0 1 0 1 1 1 0 0 p 0 1 x x x x x x bp low power 1 0 sa (3:0) 0 1 0 1 1 1 0 0 p 1 0 x x x x x x bp reserved 1 0 sa (3,0) 0 1 0 1 1 1 0 0 p 1 1 x x x x x x bp product id 1 0 sa (3,0) 0 1 0 1 1 1 0 1 p 0 0 1 0 0 0 0 0/1 bp manufacturer id 1 0 sa (3:0) 0 1 0 1 1 1 1 0 p 0 0 1 0 1 1 1 0 bp manufacturer usid 1 0 sa (3,0) 0 1 0 1 1 1 1 1 p 0 0 0 1 usid bp extended register write command sequence in order to access more than one register in one sequence this message could be used. most commonly it will be used for loading three dac registers at the same time. the four lsbs of the extended register write command frame determine the number of bytes that will be written by the command sequence. a value of 0b0000 would write one byte and a value of 0b1111 would write sixteen bytes. if more than one byte is to be written, the register address in the command sequence contains the address of the first extended register that will be written to and the slave?s local extended register address shall be automatically incremented by one for each byte written up to address 0x1f, starting from the address indicated in the address frame. figure 14. extended register write command sequence tcc?202 www. onsemi.com 19 table 16. rffe command frame for extended register write command sequence for dacs loading procedure description ssc command frame tcc?202 www. onsemi.com 20 table 20. power mode bit setting in register [0x1c] pm1 pm0 state description 0 0 active boost control active, vhv set by digital interface vout a, benabled and controlled by digital interface (default) 0 1 startup boost control active, vhv set by digital interface vout a, bdisabled 1 0 low power digital interface is active while all other circuits are in low power mode 1 1 reserved state of hardware does not change table 21. extended register write to update dac a, b description ssc command frame address frame extended registe r write tc_indx_l and dac a, b op code tcc?202 www. onsemi.com 21 following picture shows tcc?202 and all the necessary external components figure 16. tcc?202 with external components c hv vio vdda l_boost vhv tcc?2x2 i vio i vdda i ind c boost c vio c vreg vreg v batt v io r filt c vdda l boost i batt out a,b c daca,b d sch table 23. recommended external bom component function min typ max unit package c vdda analog supply decoupling capacitor 1 f 0402 c vio vio supply decoupling capacitor 100 nf 0201 c boost boost supply capacitor 1 f 0402 c hv storage/filtering capacitor for the high voltage 47 nf 0402 r filt decoupling/filtering resistor for the vbatt note* 3.3 0603 l boost boost inductor (note 15) 15 h 0603 c vreg regulator decoupling cap 220 nf 0201 c daca,b rf decoupling cap (note 16)* 100 pf 0201 d sch rectifying shottky diode (note 17) sod?923/ sod?323 *should be 50 v compliant. 15. the following inductor should be used: tdk vls2010et?150m or equivalent 16. recommended in noise reduction only? not essential but place next to ptic if used 17. the nsr0240p2t5g diode from on semiconductor and the sunlord sph201610h150mt are recommended. the nsr0340ht1g and nsr0340p2t5g devices may also be used. table 24. ordering information device package shipping ? tcc?202a?rt rdl (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. tcc?202 www. onsemi.com 22 tape & reel dimensions figure 17. wlcsp carrier tape drawings figure 18. orientation in tape assembly instructions note: it is recommended that under normal circumstances, this device and associated components should be located in a shielded enclosure. tcc?202 www. onsemi.com 23 package dimensions wlcsp12, 1.28x1.684 case 567kz issue a seating plane 0.08 c 0.10 c a1 a2 c side view note 3 a 0.25 12x dimensions: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.40 recommended a1 package outline pitch 0.40 pitch 0.05 c 2x 0.05 c 2x top view e a 0.05 b c 0.03 c 12x b 4 c b a bottom view 123 e/2 e notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to the spherical crowns of the solder balls. dim a min max ??? millimeters a1 d 1.28 bsc e b 0.23 0.29 e 0.40 bsc 0.65 0.17 0.23 1.684 bsc a2 0.38 ref on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 tcc?202/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative |
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